Silicon wafers are commonly utilized for fabricating semiconductor devices. The silicon wafers provide a semiconductor material upon which transistors and other semiconductor devices may be fabricated. Silicon wafers, however, are known to include silicon dioxide (SiO2) precipitates, crystalline originated particles (COPs), polishing defects, and vacancy defects at or near the wafer surface. As a result, silicon-on-insulator (SOI) technology has been developed to eliminate or reduce these defects. Additionally, SOI devices are able to obtain higher processing speeds and lower power consumptions. SOI devices also allow better well isolation and tighter, smaller design rules, particularly for 90 nm and below designs.
Traditional SOI integrated circuits are formed on SOI substrates. A cross-section of SOI substrate 100 is illustrated in FIG. 1a. SOI substrates typically have an active layer 110, generally formed of a thin epitaxial layer of silicon, silicon-germanium oxide, germanium, strained silicon, or the like, disposed on an insulator layer 112, such as a buried oxide (BOX) layer. The insulator layer 112 is provided on a substrate 114, typically a silicon or glass substrate. The insulator layer 112 is comprised of an insulator such as silicon dioxide, which electrically isolates the active layer 110 from the substrate 114.
FIGS. 1b-1e illustrate one example of conventional processing used to create active regions on the SOI. Generally, in an SOI chip the SOI substrate 100 is processed to form a plurality of active regions (shown in FIG. 1d) in the active layer 110. Active devices such as transistors and diodes may be formed in the active regions. Active devices in the active regions are isolated from the substrate 114 by the insulator layer 112.
FIG. 1b illustrates deposition of a hard mask 116, such as a layer of silicon dioxide (SiO2) and silicon nitride (Si3N4), upon the active layer 110. The hard mask 116 allows the formation and definition of active regions upon the insulator layer 112. In FIG. 1c, a photoresist layer 118 has been applied, exposed, and developed upon the hard mask 116. The photoresist layer 118 defines the active regions or patterns of the underlying material, i.e., the hard mask 116 and the active layer 110 in this case, that are to remain after the etching process.
FIG. 1d illustrates the resulting configuration after an etching process has been performed. A plurality of active regions 120 represent the remaining portions of the active layer 110 (see FIGS. 1a-1c) that were not etched away as part of the etching process and will be utilized to create SOI devices.
FIG. 1e illustrates the result of a wet dip process that removes the hard mask 116. Frequently, however, the wet dip process results in an undercut region 122 below the edges of the active region 120 in the insulator layer and may induce silicon defects on the sidewalls of the active region 120.
Subsequent processing steps frequently include the application of a conductive layer, such as a polysilicon or silicide, for forming transistors and the like. During the deposition of the conductive layer and subsequent patterning and etching, residue of the conductive layer typically remains in the undercut regions 122. Depositions of polysilicon or silicide in the undercut region are undesirable. In particular, the depositions of polysilicon or silicide can create a leakage path between gate-to-gate, active area-to-active area, contact-to-contact, and contact-to-active area.
Therefore, there is a need for a process to fabricate semiconductor devices, particularly semiconductor devices formed on SOI wafers, to eliminate or reduce the leakage path between gate-to-gate, active area-to-active area, contact-to-contact, and contact-to-active area and the Si defect on the sidewall of the active region.